Investigation of VDMOSFET's switching power dissipation changes under constant electrical stress

Abstract

This study aims to examine the electrical stress effects on the switching power dissipation in n-channel VDMOSFET. We set up a resistive load NMOS inverter as a WA circuit. At first step of measurement, VDMOSFETs are subjected to the high constant voltage (55V(DC)) up to 6 h and this degradation process is continued until just prior to the oxide breakdown. Stress induced changes in output voltage and current are extracted using the resistive load NMOS inverter. The static and dynamic power dissipations, and power-delay product are calculated accordingly. In addition, assuming that the inverter load is selected as n-channel VDMOSFET, the power dissipation is calculated. In resistive load NMOS inverter, it is observed that the static power dissipation is decreased by 5.3%, the dynamic power is increased by around 60% and the total power dissipation is decreased by 5% compared to before the stress. In enhancement load NMOS inverter, the total power dissipation has a decrease of around 92%.